Recent developments in multimedia applications such as, cell phones, PDA, digital camera, etc. have increasingly required memory devices with higher density. Conventional memories include dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory (NVM). Non-volatile memory may include mask read only memory (ROM), electrically erasable programmable read only memory (EEPROM), and flash memory. Non-volatile memory does not lose data when power is lost, but is generally does not permit random access and is slower than volatile memory.
Flash memory may be formed by a combination of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). Flash memory may be NAND or NOR flash memory. Erase and program operations may be performed in a flash memory by the application of different voltages to each flash memory cell.
Due to the increased demand for high density memory, flash memory, such as flash EEPROM, has been used in an auxiliary memory or in system programming applications where continuous updating is needed. Flash EEPROM also may have a higher integration degree than conventional EEPROM.
However, flash memory may have read errors due to coupling noise between sense lines of a page buffer. To reduce coupling noise and the resulting read errors, a space between sense nodes may be increased, or a signal line (for example, a VDD or a VSS line) may be inserted between sense lines. Both of these solutions have the drawback of requiring increased memory chip size and/or increased manufacturing costs.
Referring to FIG. 1, a conventional flash memory device, such as a NAND-type flash memory device may include a memory cell array 10 for storing data. The memory cell array 10 may include a plurality of cell strings (which may be referred to as NAND strings) that are connected to corresponding bit lines. Each cell string may include a string select transistor connected to a corresponding bit line, a ground select transistor connected to a common source line, and memory cells connected serially between the string and ground select transistors.
FIG. 1 illustrates four pairs of bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O), however, any number (usually many more than four) of bit lines may be connected to the memory cell array 10. Each bit line pair may be electrically connected to a corresponding page buffers PB0, PB1, PB2, and PB3.
Each of the page buffers PB0, PB1, PB2, and PB3 may act as a sense amplifier for a read/verify operation and as a driver for driving a bit line according to data to be programmed for a program operation. The page buffers PB0, PB1, PB2, and PB3 may be identical, therefore, constituent elements of the page buffers PB0, PB1, PB2, and PB3 are indicated by the same reference symbols, and the configuration of only one page buffer (e.g. PB0) need be described.
The page buffer PB0 may include a bit line select and bias circuit 22, a pre-charge circuit 24, and a sense and latch circuit 26. The bit line select and bias circuit 22 may include NMOS transistors HT0, HT1, HT2, and HT3. The NMOS transistor HT0 may be connected between a power line VIRPWR and a bit line BL0_E and controlled by a control signal VBLe. The NMOS transistor HT1 may be connected between the power line VIRPWR and a bit line BL0_O and controlled by a control signal VBLo. The NMOS transistor HT2 may be connected between the bit line BL0_E and a sense node SO0, and the NMOS transistor HT3 may be connected between the bit line BL0_O and the sense node SO0. The NMOS transistors HT2 and HT3 may be controlled by control signals BLSLTe and BLSLTo, respectively. Each of the NMOS transistors HT0-HT3 may be a high-voltage transistor having a breakdown voltage, for example, of about 28V.
The pre-charge circuit 24 may include a PMOS transistor LT0, which may be connected between a power supply voltage and the sense node SO0 (which may also be referred to as a sense line) and controlled by a control signal PLOAD.
The sense and latch circuit 26 may include NMOS transistors LT1, LT2, and LT3 and a latch LAT including inverters INV0 and INV1. The NMOS transistors LT2 and LT3 may be serially connected between a latch node N2 of the latch LAT and a ground voltage. A gate of the NMOS transistor LT2 may be electrically connected to the sense node SO0 and a gate of the NMOS transistor LT3 may connected to receive a control signal PBLCH. The NMOS transistor LT1 may be electrically connected between the sense node SO0 and a latch node N1 of the latch LAT and controlled by a control signal LCHDRV. The latch node N1 may be used as a page buffer data input/output node PB_DIO0, which is connected to a column decoder 60. Each of the NMOS transistors LT0–LT3 and PMOS and the NMOS transistors that make up the inverters INV0 and INV1 may be a low-voltage transistor having a breakdown voltage, for example, of about 7V.
As describe above, higher-voltage transistors may be used in the bit line select and bias circuit 22 of each page buffer PB0, PB1, PB2, and PB3. This may be because a higher voltage (for example, about 20V) applied to a bulk region of the memory cell array 10 may be transferred to the bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O), via source regions of the string select transistors of the memory array 10. For this reason, the NMOS transistors HT2 and HT3 in each page buffer PB0, PB1, PB2, and PB3 may be composed of higher-voltage transistors to prevent a higher voltage from being transferred to the corresponding pre-charge circuit 24 and sense and latch circuit 26.
Similarly, the NMOS transistors HT0 and HT1 in each page buffer PB0, PB1, PB2, and PB3 may be composed of higher-voltage transistors that can withstand higher voltages transferred to the corresponding bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O), during an erase operation.
A high-voltage transistor may be formed to have a breakdown voltage of about 28V, while a low-voltage transistor may be formed in a P-type/N-type well to have a breakdown voltage of about 7V. Hereinafter, a region where higher-voltage transistors are formed will be referred to as a high-voltage region (or a high-voltage circuit region), and a region where lower-voltage transistors are formed will be referred to as a low-voltage region (or a low-voltage circuit region).
In each page buffer PB0, PB1, PB2, and PB3, NMOS transistors of a corresponding bit line select and bias circuit 22 may be formed in a high-voltage region and MOS transistors of a corresponding pre-charge circuit 24 and sense and latch circuit 26 may be formed in a low-voltage region.
For example, referring to FIG. 2a, which illustrates a timing diagram for describing a read operation of the flash memory of FIG. 1 and FIG. 2b, which illustrates an example layout of the page buffers PB0, PB1, PB2, and PB3 of FIG. 1, constituent elements (i.e. high-voltage transistors) of the bit line select and bias circuit 22 in page buffer PB0 may be disposed in a high-voltage region 30, and constituent elements (i.e. low-voltage transistors) of the pre-charge circuit 24 and sense and latch circuit 26 in the page buffer PB0 may be disposed in a low-voltage region 32. Similarly, constituent elements (i.e. high-voltage transistors) of the bit line select and bias circuit 22 of page buffer PB1 may also be disposed in a high-voltage region 34 and constituent elements (i.e. low-voltage transistors) of the pre-charge circuit 24 and sense and latch circuit 26 of page buffer PB1 may be disposed in a low-voltage region 36. High-voltage transistors of other page buffers, for example, PB2, PB3, etc. may also be disposed in corresponding high-voltage regions 38, 42, etc. and low-voltage transistors of the other page buffers may also be disposed in corresponding low-voltage regions 40, 44, etc.
As illustrated in FIG. 2b, the high-voltage regions 30, 34, 38, and 42 may be collectively arranged closer to the bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O) and the low-voltage regions 32, 36, 40, 44 may be collectively arranged further away from the bit lines (BL0_E, BL0_O), (BL1_E, BL1_O), (BL2_E, BL2_O) and (BL3_E, BL3_O). An advantage of such an arrangement is that it enables repetition of a well space between the high-voltage region and the low-voltage region to be reduced. If an arrangement such as the one illustrated in FIG. 2b is not utilized, a well space between a high-voltage region and a low-voltage region must be repeated, thus increasing layout size.
However, using the page buffer layout of FIG. 2b, for sense nodes of page buffers PB0, PB1, PB2, and PB3, sense lines SO0, SO1, SO2, and SO3 may be extended from the high-voltage regions 30, 34, 38, and 42 into the low-voltage regions 32, 36, 40, 44. This layout may cause a read error, which is more clearly illustrated in FIG. 2a. 
As described above, FIG. 2a illustrates a timing diagram for a read operation of a flash memory device, such as the device of FIG. 1. As shown, a read operation of a flash memory device may include a page buffer reset interval T0, a bit line pre-charge interval T1, a sense interval T2, and a latch interval T3. Each interval is described in more detail below.
In the page buffer reset interval T0, control signals VBLe, VBLo, BLSLTe, BLSLTo, LCHDRV, and PLOAD may be set to a first level (for example, a “high” level) and a ground voltage may be supplied to a power line VIRPWR. This makes bit lines BLi_E and BLi_O (i=0–3) and latch nodes N1 connected to the power line VIRPWR. The bit lines BLi_E and BLi_O and the latch nodes N1 may be set to the ground voltage; that is, the bit lines BLi_E and BLi_O and the latch nodes N1 may be reset in the page buffer reset interval T0.
Assuming that the even-numbered bit lines BLi_E of the bit lines pairs are selected and the odd-numbered bit lines BLi_O thereof are unselected, in the bit line pre-charge interval T1, the control signals VBLe, BLSLTo, LCHDRV, and PLOAD may be set to a second level (for example, a “low” level), while the control signal VBLo continues to be maintained at the first level (high). The control signal BLSLTe may be set to have a voltage of about 1.5V.
Under these conditions, the unselected bit lines BLi_O may be electrically connected to the power line VIRPWR through NMOS transistors HT1 of corresponding bit line select and bias circuits 22. That is, discharged voltages on the unselected bit lines BLi_O may be maintained.
At the same time, as PMOS transistors LT0 of page buffers PB0–PB3 may be turned on and the sense nodes SO0–SO3 may be charged with a power supply voltage. Since the control signal BLSLTe having a voltage of about 1.5V is applied to the gates of NMOS transistors HT2 of the page buffers PB0–PB3, selected bit lines BLi_E are pre-charged with a voltage of (1.5V-Vth) (where Vth is a threshold voltage of an NMOS transistor). For example, the selected bit lines BLi_E may be pre-charged with about 0.8V.
In the sense interval T2, the control signals VBLe, VBLo, BLSLTo, LCHDRV, and PLOAD may be maintained at the same conditions as in the bit line pre-charge interval T1, while the control signal BLSLTe is set to a second (low) level. This turn off NMOS transistors HT2 of the page buffers PB0–PB3. In this state, pre-charged voltages on the selected bit lines BLi_E may be maintained or lowered according to a state (an “on” state or an “off” state) of memory cells connected to the selected bit lines BLi_E. Assuming that memory cells of an on state are connected to the selected bit lines BL0_E, BL2_E, and BL3_E and a memory cell of an off state is connected to the selected bit line BL1_E, as illustrated in FIG. 2a, the pre-charged voltages on the bit lines BL0_E, BL2_E, and BL3_E may be lowered to a ground voltage while the pre-charged voltage on the bit line BL1_E may be maintained.
As the control signal PLOAD is set to a first (high) level in the latch interval T3, PMOS transistors LT0 of the page buffers PB0–PB3 may be turned off, so that the sense nodes SO0, SO1, SO2, and SO3 “float”. In this condition, a voltage of about 1.0V is applied to the control signal BLSLTe. Because the pre-charged voltage on the bit line BL1_E is maintained, an NMOS transistor HT2 of the page buffer PB1 is shut off. This is because a gate-source voltage Vgs (Vgs=1.0V−0.8V=0.2V) of the NMOS transistor HT2 in the page buffer PB1 is lower than a threshold voltage (0.7V). On the other hand, since the pre-charged voltages on the bit lines BL0_E, BL2_E, and BL3_E are discharged through memory cells of an on state, NMOS transistors HT2 of the other page buffers PB0, PB2, and PB3 are turned on. Voltages on sense nodes SO0, SO2, and SO3 may be discharged from the power supply voltage to the ground voltage, while a voltage on the sense node SO1 is maintained.
This forces an NMOS transistor LT2 connected to the sense node SO1 to be turned on and NMOS transistors LT2 connected to the sense nodes SO0, SO2, and SO3 to be turned off. Afterward, as illustrated in FIG. 2a, when the control signal PBLCH is pulsed, values of latches LT in the page buffers PB0–PB3 are determined according to voltages on the sense nodes SO0–SO3.
As described above, voltages on the sense nodes SO0–SO3 may be selectively changed from a power supply voltage to a ground voltage at a floating state. A sense node in a floating state may be affected by voltage variations of an adjacent sense node through, for example, coupling capacitance.
As illustrated in FIG. 2b, because adjacent sense nodes (or sense lines) may be laid out to overlap in a direction vertical to a bit line, coupling capacitance (in FIG. 2b, C0–C3) may exist between adjacent sense lines.
When a voltage on a sense node SO1 of a floating state is lowered by a corresponding voltage to a coupling ratio (α) of a coupling capacitance when voltages on adjacent sense nodes SO0 and SO2 are changed from a power supply voltage to a ground voltage. This may be referred to as coupling noise or sense noise.
If a voltage on the sense node SO1 of a floating state becomes lower than a trip voltage of an NMOS transistor LT2 due to the coupling noise, erroneous data may be latched in a latch LAT when the control signal PBLCH is pulsed. As a result, with a page buffer layout arrangement as shown in FIG. 2, a read error may be caused by the coupling noise between adjacent sense lines (or nodes).